Untitled Document

Paste from Guest at 2010-11-27 00:41:24 | Syntax: | Hits: 95 | Valid for: Never

1234567891011121314151617181920212223242526272829303132333435363738394041424344454647484950515253545556575859606162636465666768697071727374757677787980818283848586878889909192939495969798
Index: firmware/export/s5l8700.h
===================================================================
--- firmware/export/s5l8700.h	(revision 28675)
+++ firmware/export/s5l8700.h	(working copy)
@@ -25,7 +25,7 @@
 #define REG16_PTR_T volatile uint16_t *
 #define REG32_PTR_T volatile uint32_t *
 
-#define TIMER_FREQ  47923200L
+#define TIMER_FREQ  (CPUFREQ_DEFAULT)
 
 #define CACHEALIGN_BITS (4) /* 2^4 = 16 bytes */
 
Index: firmware/target/arm/s5l8700/system-target.h
===================================================================
--- firmware/target/arm/s5l8700/system-target.h	(revision 28675)
+++ firmware/target/arm/s5l8700/system-target.h	(working copy)
@@ -25,9 +25,9 @@
 #include "mmu-arm.h"
 
 #define CPUFREQ_SLEEP      32768
-#define CPUFREQ_DEFAULT 47923200
-#define CPUFREQ_NORMAL  47923200
-#define CPUFREQ_MAX    191692800
+#define CPUFREQ_MAX     (1843200 * 2 * 109 / 2) /* 200.9 MHz */
+#define CPUFREQ_DEFAULT (CPUFREQ_MAX/8)
+#define CPUFREQ_NORMAL  (CPUFREQ_MAX/8)
 
 #define STORAGE_WANTS_ALIGN
 
Index: firmware/target/arm/s5l8700/crt0.S
===================================================================
--- firmware/target/arm/s5l8700/crt0.S	(revision 28675)
+++ firmware/target/arm/s5l8700/crt0.S	(working copy)
@@ -131,7 +131,7 @@
     mov r0, #0
     str r0, [r1,#0x24]  // PLLCON
 #ifdef IPOD_NANO2G
-    ldr r0, =0x21200    // pdiv=2, mdiv=0x12 sdiv=0
+    ldr r0, =0x006501    // pdiv=0, mdiv=0x65 sdiv=1, 201 MHz
 #else
     ldr r0, =0x1ad200   // pdiv=0x1a, mdiv=0xd2 sdiv=0
 #endif
@@ -146,7 +146,7 @@
     ldr r0, [r1,#0x20]  // PLLLOCK
     tst r0, #1
     beq 1b
-    mov r0, #0x280
+    mov r0, #0x480      // 0x480 = HCLK / 4
     str r0, [r1,#0x3c]  // CLKCON2
     ldr r0, =0x20803180 // FCLK_CPU = 200MHz, HCLK = 100MHz, PCLK = 50MHz, other clocks off
     str r0, [r1]        // CLKCON
Index: firmware/target/arm/s5l8700/kernel-s5l8700.c
===================================================================
--- firmware/target/arm/s5l8700/kernel-s5l8700.c	(revision 28675)
+++ firmware/target/arm/s5l8700/kernel-s5l8700.c	(working copy)
@@ -44,7 +44,10 @@
     
     /* configure timer for 10 kHz */
     TBCMD = (1 << 1);   /* TB_CLR */
-    TBPRE = 300 - 1;    /* prescaler */
+//    TBPRE = 300 - 1;    /* prescaler 48 MHz */
+//    TBPRE = 200 - 1;    /* prescaler 32 MHz */
+//    TBPRE = 150 - 1;    /* prescaler 24 MHz */
+    TBPRE = 157 - 1;    /* prescaler 25 MHz */
     TBCON = (0 << 13) | /* TB_INT1_EN */
             (1 << 12) | /* TB_INT0_EN */
             (0 << 11) | /* TB_START */
Index: firmware/target/arm/s5l8700/system-s5l8700.c
===================================================================
--- firmware/target/arm/s5l8700/system-s5l8700.c	(revision 28675)
+++ firmware/target/arm/s5l8700/system-s5l8700.c	(working copy)
@@ -212,8 +212,8 @@
         udelay(100);
         /* FCLK_CPU = PLL0, HCLK = PLL0 / 2 */
         CLKCON = (CLKCON & ~0xFF00FF00) | 0x20003100;
-        /* PCLK = HCLK / 2 */
-        CLKCON2 |= 0x200;
+        /* PCLK = HCLK / 4 */
+        CLKCON2 |= 0x400;
         /* Switch to ASYNCHRONOUS mode => GCLK = FCLK_CPU */
         asm volatile(
             "mrc     p15, 0, r0,c1,c0    \n\t"
@@ -232,9 +232,10 @@
             ::: "r0"
           );
         /* PCLK = HCLK */
-        CLKCON2 &= ~0x200;
-        /* FCLK_CPU = OFF, HCLK = PLL0 / 4 */
-        CLKCON = (CLKCON & ~0xFF00FF00) | 0x80003300;
+        CLKCON2 &= ~0x400;
+        /* FCLK_CPU = OFF, HCLK = PLL0 / 8 */
+        CLKCON = (CLKCON & ~0xFF00FF00) | 0x80003700;
+
         /* Vcore = 0.900V */
         pmu_write(0x1e, 0xb);
     }


» no title
« no title